Turning to FIGS. 1 and 2, a conventional multi-channel data converter system 100 can be seen. This system 100 generally comprises a multiplexer or mux 102, an ADC 104 (which can be a successive approximation register or SAR ADC operating at 250 kSPS), boost logic 106, and select logic 108. Typically, mux 102 receives several analog input signals IN1 to INN so as to provide ADC 104 with a multiplexed analog signal that is converted (by ADC 104) to a digital output signal DOUT. Boost logic 106 and select logic 108 generally perform the interleaving of the analog input signals IN1 to INN (using select signals SEL1 to SELN) based on the sample signal SAMPLE. Mux 102 (which can be seen in greater detail in FIG. 2) is generally comprised of cells 202-1 to 202-N (where each corresponds to a channel of mux 102). Each cell 202-1 to 202-N generally and respectively comprises switches S1-1 to S5-1 through S1-N to S5-N, a capacitor C1 to CN, transistors Q1-1 to Q3-1 through Q1-N to Q3-N (which are each generally NMOS transistors), and transmission gates 204-1/206-1 to 204-N/206-N.
As can be seen from system 100, the operation of mux 102 (which can be seen in greater detail in FIG. 2) is generally dependant on the phase of the sample signal SAMPLE. Initially, capacitors C1 to CN are charged to the voltage on positive rail HPVDD by deasserting select signals SEL1-A to SELN-A and asserting select signals SEL1-B to SELN-B. Following the charging of capacitors C1 to CN and as an example, if it is assumed that channel 1 (cell 202-1) is selected, then the select signal SEL1-A is asserted, while SEL1-B (and SEL2-A/SEL2B to SELN-A/SELN-B) are deasserted. This allows the voltage from input signal IN1 at the sampling instant plus the voltage stored on capacitor C1 (i.e., +15V) to initially be applied to the gates of switches Q1-1 and Q2-1. As the boosted voltage is applied, the input signal's IN1 voltage at the sampling instant is transmitted through the switch Q1-1 and transmission gate 204-1 to switch Q2-1 and transmission gate 206-1 (which generally perform the same function as switch Q1-1 and transmission gate 204-1). The switches Q2-1/Q3-1 to Q2-N/Q3-N and transmission gates 206-1 are generally provided to reduce crosstalk because these components generally eliminate the parasitic capacitance between the input and output.
While the cells 202-1 to 202-N generally do reduce crosstalk (in part because of the grounding provided through switches Q3-1 to Q3-N), there are some drawbacks. Namely, the repetition of switches Q2-1 to Q2-N can be problematic. Because switches Q1-1/Q2-1 to Q1-N/Q2-N are large to reduce input resistance at high frequency operation, these switches occupy a considerable amount of area. Moreover, the series switches Q1-1/Q2-1 to Q1-N/Q2-N limit the operating speed of ADC 104. Therefore, there is need for an improved mux.
Some examples of conventional circuits are: U.S. Pat. Nos. 6,404,237; 7,064,599; 7,268,610; 7,471,135; and U.S. Patent Pre-Grant Publ. No. 2002/0175740.